1. Field of the Invention
The invention relates to automatic test equipment used to test integrated circuits. In particular, the invention is directed to a method and apparatus for dynamically controlling the timing of signals in such test equipment, including synchronizing or deskewing a plurality of signals to be supplied to, or received from, an integrated circuit being tested.
2. Description of the Prior Art
With the development of increasingly complicated integrated circuits there is a corresponding increase in the demands made upon test equipment used for quality control or evaluation of the completed devices. An example of such test equipment is the automated Sentry.RTM. series of testers manufactured by Fairchild Camera & Instrument Corporation. In automatic test equipment input signals are applied to selected pins of an integrated circuit being tested (usually known as device under test), which in response produces output signals at other selected pins. The test equipment automatically senses the response of the device under test and analyzes the response signals for their compliance with quality-control standards.
In general, the automatic test equipment has the capabilities of applying a precisely controlled preprogrammed electrical signal to desired pins of the device under test and analyzing the response signals from desired pins. With recent advancements in technology, integrated circuits may have hundreds of pins. Consequently, the test equipment may have hundreds of duplicate driver and comparator circuits, one or more of each being associated with each pin of the circuit being tested. The test equipment also includes timing generators for supplying timing information for the test signals to be applied to the pins, and formatting circuits for producing patterns of test signals.
Under control of the test system computer and its programs, the test equipment can perform tests on a variety of integrated circuit devices. In each test an array of stimuli signals are applied to pins of the device under test, and the array of responses analyzed. Generally, the stimuli signals travel to each pin by a different path in the system. Similarly, the response signals from the device under test follow different paths from the output pins to the circuitry where the signals are analyzed. Because of the substantial differences in propagation delay and other detrimental influences on signal timing, it is essential to precisely control the timing of signals which are desired to arrive at the device under test at precise times or in synchronization or to be received from such device. In addition it is desirable to control the timing of signals more precisely than specified than by the clock generator of the system. Timing variations which adversely impact these goals must be corrected to assure the validity of the tests performed.
Timing errors of all types, other than cross-talk, are collectively termed "skew" herein. In an early approach to deskewing signals, a number of manually adjustable potentiometer were associated with each pin for aligning the signals. The potentiometers were readjusted whenever the equipment required recalibration, often daily or more frequently. Obviously the time and labor involved render this approach extremely undesirable.
Another approach, not necessarily in the prior art, but described herein to enable better understanding of this invention, is described in copending U.S. Pat. No. 4,488,297, U.S. Pat. No. 4,488,297 entitled "Programmable Deskewing of Automatic Test Equipment", and assigned to the same assignee as the present invention, provides a system which can be programmed, in conjunction with a predetermined test, to automatically deskew the stimuli and response signals. Generally, that system includes a coarse deskew unit for rough adjustment followed by a fine deskew unit for fine adjustment. The coarse deskew unit includes a plurality of logic gates and a multiplexer. The coarse delay is determined by the number of gates through which the signal is transmitted. The fine deskew unit includes a delay line tapped along its length at intermediate intervals for connection to successive inputs of a multiplexer. After being transmitted through an appropriate number of gates to generate the coarse delay, the signal is supplied to the delay line in the fine deskew unit, and the appropriate input selectively connected to the multiplexer output. In this manner a plurality of discrete delay times can be achieved by selecting the number of delay-line segments through which the signal passes.